A word is two contiguous bytes starting at any byte address. A word thus contains 16 bits. The bits of a word are numbered from 0 through 15; bit 0 is the least significant bit. The byte containing bit 0 of the word is called the low byte; the byte containing bit 15 is called the high byte.
Each byte within a word has its own address, and the smaller of the addresses is the address of the word. The byte at this lower address contains the eight least significant bits of the word, while the byte at the higher address contains the eight most significant bits.
A doubleword is two contiguous words starting at any byte address. A doubleword thus contains 32 bits. The bits of a doubleword are numbered from 0 through 31; bit 0 is the least significant bit. The word containing bit 0 of the doubleword is called the low word; the word containing bit 31 is called the high word.
Each byte within a doubleword has its own address, and the smallest of the addresses is the address of the doubleword. The byte at this lowest address contains the eight least significant bits of the doubleword, while the byte at the highest address contains the eight most significant bits. Figure 2-3 illustrates the arrangement of bytes within words anddoublewords.
Note that words need not be aligned at even-numbered addresses and doublewords need not be aligned at addresses evenly divisible by four. This allows maximum flexibility in data structures (e.g., records containing mixed byte, word, and doubleword items) and efficiency in memory utilization. When used in a configuration with a 32-bit bus, actual transfers of data between processor and memory take place in units of doublewords beginning at addresses evenly divisible by four; however, the processor converts requests for misaligned words or doublewords into the appropriate sequences of requests acceptable to the memory interface. Such misaligned data transfers reduce performance by requiring extra memory cycles. For maximum performance, data structures (including stacks) should be designed in such a way that, whenever possible, word operands are aligned at even addresses and doubleword operands are aligned at addresses evenly divisible by four. Due to instruction prefetching and queuing within the CPU, there is no requirement for instructions to be aligned on word or doubleword boundaries. (However, a slight increase in speed results if the target addresses of control transfers are evenly divisible by four.)
Although bytes, words, and doublewords are the fundamental types of operands, the processor also supports additional interpretations of these operands. Depending on the instruction referring to the operand, the following additional data types are recognized:
up:
Chapter 2 -- Basic Programming ModelFigure 2-1. Two-Component Pointer
* *
| |
|---------------|-+
32 0 | | |
+-------+-------+ +---+ |---------------| |
| OFFSET |---| + |--->| OPERAND | |
+-------+-------+ +---+ |---------------| |- SELECTED SEGMENT
^ | | |
16 0 | | | |
+-------+ | | | |
|SEGMENT|---------.----->|---------------|-+
+-------+ | |
| |
| |
* *
Figure 2-2. Fundamental Data Types
7 0
+---------------+
| BYTE | BYTE
+---------------+
15 7 0
+---------------+---------------+
| HIGH BYTE | LOW BYTE | WORD
+---------------+---------------+
address n+1 address n
31 23 15 7 0
+---------------+---------------+---------------+--------------+
| HIGH WORD | LOW WORD | DOUBLEWORD
+---------------+---------------+---------------+--------------+
address n+3 address n+2 address n+1 address n
Figure 2-3. Bytes, Words, and Doublewords in Memory
MEMORY
BYTE VALUES
All values in hexadecimal
ADDRESS +----------+
E| |
|----------|--+
D| 7A | |- DOUBLE WORD AT ADDRESS A
|----------|-+| CONTAINS 7AFE0636
C| FE | ||
|----------| |- WORD AT ADDRESS B
B| 06 | || CONTAINS FE06
|----------|-+|
A| 36 | |
|----------|--|
9| 1F | |- WORD AT ADDRESS 9
|----------|--+ CONTAINS IF
8| |
|----------|--+
7| 23 | |
|----------| |- WORD AT ADDRESS 6
6| OB | | CONTAINS 23OB
|----------|--+
5| |
|----------|
4| |
|----------|--+
3| 74 | |
|----------|-+|- WORD AT ADDRESS 2
2| CB | || CONTAINS 74CB
|----------|--+
1| 31 | |-- WORD AT ADDRESS 1
|----------|-+ CONTAINS CB31
0| |
+----------+
Figure 2-4. 80386 Data Types
+1 0
7 0 7 0 15 14 8 7 0
BYTE +++++++++ BYTE +++++++++ WORD +++++++++++++++++
INTEGER || | | ORDINAL | | | INTEGER || | | | |
++------+ +-------+ ++------+-------+
SIGN BIT++------+ +-------+ SIGN BIT++MSB |
MAGNITUDE MAGNITUDE +---------------+
MAGNITUDE
+1 0 +3 +2 +1 0
15 0 31 16 15 0
WORD +++++++++++++++++ DOUBLEWORD +++++++++++++++++++++++++++++++++
ORDINAL || | | | | INTEGER || | | | | | | | |
++------+-------+ ++------+-------+-------+-------+
| | SIGN BIT++MSB |
+---------------+ +-------------------------------+
MAGNITUDE MAGNITUDE
+3 +2 +1 0
31 0
DOUBLEWORD +++++++++++++++++++++++++++++++++
ORDINAL | | | | | | | | |
+-------+-------+-------+-------+
+-------------------------------+
MAGNITUDE
+N +1 0
7 0 7 0 7 0
BINARY CODED +++++++++ +++++++++++++++++
DECIMAL (BCD) | | | *** | | | | |
+-------+ +-------+-------+
BCD BCD BCD
DIGIT N DIGIT 1 DIGIT 0
+N +1 0
7 0 7 0 7 0
PACKED +++++++++ +++++++++++++++++
BCD | | | *** | | | | |
+-------+ +-------+-------+
+---+ +---+
MOST LEAST
SIGNIFICANT SIGNIFICANT
DIGIT DIGIT
+N +1 0
7 0 7 0 7 0
BYTE +++++++++ +++++++++++++++++
STRING | | | *** | | | | |
+-------+ +-------+-------+
-2 GIGABYTES
+2 GIGABYTES 210
BIT +++++------------++------- ----------------+++++
STRING ||||| || |||||
+++++------------++-------- ---------------+++++
BIT 0
+3 +2 +1 0
31 0
NEAR 32-BIT +++++++++++++++++++++++++++++++++
POINTER | | | | | | | | |
+-------+-------+-------+-------+
+-------------------------------+
OFFSET
+5 +4 +3 +2 +1 0
48 0
FAR 48-BIT +++++++++++++++++++++++++++++++++++++++++++++++++
POINTER | | | | | | | | | | | | |
+-------+-------+-------+-------+-------+-------+
+---------------+-------------------------------+
SELECTOR OFFSET
+5 +4 +3 +2 +1 0
32-BIT +++++++++++++++++++++++++++++++++++++++++++++++++
BIT FIELD | | | | | | | | | | | | |
+-------+-------+-------+-------+-------+-------+
|<--------- BIT FIELD --------->|
1 TO 32 BITS
prev: 2.1 Memory Organization and Segmentation
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