The 80386 invokes an interrupt or exception handling procedure in much the same manner as it CALLs a procedure; the differences are explained in the following sections.
Figure 9-4. Interrupt Vectoring for Procedures
IDT EXECUTABLE SEGMENT
+---------------+ +---------------+
| | OFFSET| |
|---------------| +------------------------->| ENTRY POINT |
| | | LDT OR GDT | |
|---------------| | +---------------+ | |
| | | | | | |
INTERRUPT |---------------| | |---------------| | |
ID----->| TRAP GATE OR |--+ | | | |
|INTERRUPT GATE |--+ |---------------| | |
|---------------| | | | | |
| | | |---------------| | |
|---------------| +-->| SEGMENT |-+ | |
| | | DESCRIPTOR | | | |
|---------------| |---------------| | | |
| | | | | | |
|---------------| |---------------| | | |
| | | | |BASE| |
+---------------+ |---------------| +--->+---------------+
| |
| |
| |
+---------------+
9.6.1.1 Stack of Interrupt Procedure
Just as with a control transfer due to a CALL instruction, a control
transfer to an interrupt or exception handling procedure uses the stack to
store the information needed for returning to the original procedure. As
Figure 9-5
shows, an interrupt pushes the EFLAGS register onto the stack
before the pointer to the interrupted instruction.
Certain types of exceptions also cause an error code to be pushed on the stack. An exception handler can use the error code to help diagnose the exception.
Figure 9-5. Stack Layout after Exception of Interrupt
WITHOUT PRIVILEGE TRANSITION
D O 31 0 31 0
I F |-------+-------| |-------+-------|
R |#######|#######| OLD |#######|#######| OLD
E E |-------+-------| SS:ESP |-------+-------| SS:ESP
C X |#######|#######| | |#######|#######| |
T P |-------+-------|<----+ |-------+-------|<----+
I A | OLD EFLAGS | | OLD EFLAGS |
O N |-------+-------| |-------+-------|
N S |#######|OLD CS | NEW |#######|OLD CS |
I |-------+-------| SS:ESP |-------+-------|
| O | OLD EIP | | | OLD EIP | NEW
| N |---------------|<----+ |---------------| SS:ESP
| | | | ERROR CODE | |
! * * |---------------|<----+
* * | |
* *
WITHOUT ERROR CODE WITH ERROR CODE
WITH PRIVILEGE TRANSITION
D O 31 0 31 0
I F +-------+-------+<----+ +-------+-------+<----+
R |#######|OLD SS | | |#######|OLD SS | |
E E |-------+-------| SS:ESP |-------+-------| SS:ESP
C X | OLD ESP | FROM TSS | OLD ESP | FROM TSS
T P |---------------| |---------------|
I A | OLD EFLAGS | | OLD EFLAGS |
O N |-------+-------| |-------+-------|
N S |#######|OLD CS | NEW |#######|OLD CS |
I |-------+-------| SS:EIP |-------+-------|
| O | OLD EIP | | | OLD EIP | NEW
| N |---------------|<----+ |---------------| SS:ESP
| | | | ERROR CODE | |
! * * |---------------|<----+
* * | |
* *
WITHOUT ERROR CODE WITH ERROR CODE
9.6.1.3 Flags Usage by Interrupt Procedure
Interrupts that vector through either interrupt gates or trap gates cause
TF (the trap flag) to be reset after the current value of TF is saved on the
stack as part of EFLAGS. By this action the processor prevents debugging
activity that uses single-stepping from affecting interrupt response. A
subsequent IRET instruction restores TF to the value in the EFLAGS image on
the stack.
The difference between an interrupt gate and a trap gate is in the effect on IF (the interrupt-enable flag). An interrupt that vectors through an interrupt gate resets IF, thereby preventing other interrupts from interfering with the current interrupt handler. A subsequent IRET instruction restores IF to the value in the EFLAGS image on the stack. An interrupt through a trap gate does not change IF.
Because occurrence of interrupts is not generally predictable, this privilege rule effectively imposes restrictions on the privilege levels at which interrupt and exception handling procedures can execute. Either of the following strategies can be employed to ensure that the privilege rule is never violated.
When an interrupt or exception vectors to a task gate in the IDT, a task switch results. Handling an interrupt with a separate task offers two advantages:
If the task switch is caused by an exception that has an error code, the processor automatically pushes the error code onto the stack that corresponds to the privilege level of the first instruction to be executed in the interrupt task.
When interrupt tasks are used in an operating system for the 80386, there are actually two schedulers: the software scheduler (part of the operating system) and the hardware scheduler (part of the processor's interrupt mechanism). The design of the software scheduler should account for the fact that the hardware scheduler may dispatch an interrupt task whenever interrupts are enabled.
up:
Chapter 9 -- Exceptions and InterruptsFigure 9-6. Interrupt Vectoring for Tasks
IDT GDT
+----------------+ +----------------+
| | | | TSS
|----------------| |----------------| +----------------+
| | | | | |
|----------------| |----------------| | |
| | | | | |
|----------------| |----------------| | |
+-->| TASK GATE |---+ | | | |
| |----------------| | |----------------| | |
| | | +--->| TSS DESCRIPTOR |---+ | |
| |----------------| |----------------| | | |
| | | | | | | |
| |----------------| |----------------| +-->+----------------+
| | | | |
| |----------------| |----------------|
| | | | |
| +----------------+ +----------------+
|
+-INTERRUPT ID
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