Note
This TLB testing mechanism is unique to the 80386 and may not be
continued in the same way in future processors. Sortware that uses
this mechanism may be incompatible with future processors.
When testing the TLB it is recommended that paging be turned off (PG=0 in CR0) to avoid interference with the test data being written to the TLB.
The test command register (TR6) contains a command and an address tag to use in performing the command:
The meaning of these pairs of bits is given by Table 10-1, where X represents D, U, or W.
Table 10-1. Meaning of D, U, and W Bit Pairs X X# Effect during Value of bit X TLB Lookup after TLB Write 0 0 (undefined) (undefined) 0 1 Match if X=0 Bit X becomes 0 1 0 Match if X=1 Bit X becomes 1 1 1 (undefined) (undefined)
up:
Chapter 10 -- InitializationFigure 10-3. TLB Structure
+-----------------+----------------+
7| TAG | DATA |
|-----------------+----------------|
* * *
+------- * * *
| SET 11 * * *
| +-- |-----------------+----------------|
| | 1| TAG | DATA |
| | |-----------------+----------------|
| | 0| TAG | DATA |
| | +-----------------+----------------+
| |
| | +-----------------+----------------+
| | 7| TAG | DATA |
| | |-----------------+----------------|
| | * * *
| +-- * * *
| SET 10 * * *
| +-- |-----------------+----------------|
| | 1| TAG | DATA |
| D | | | |-----------------+----------------|
| A | | | 0| TAG | DATA |
| T +------+ | +-----------------+----------------+
| A |
| +------+ | +-----------------+----------------+
| B | | | 7| TAG | DATA |
| U | | | |-----------------+----------------|
| S | | | * * *
| +-- * * *
| SET 01 * * *
| +-- |-----------------+----------------|
| | 1| TAG | DATA |
| | |-----------------+----------------|
| | 0| TAG | DATA |
| | +-----------------+----------------+
| |
| | +-----------------+----------------+
| | 7| TAG | DATA |
| | |-----------------+----------------|
| | * * *
| +-- * * *
| SET 00 * * *
+------- |-----------------+----------------|
1| TAG | DATA |
|-----------------+----------------|
0| TAG | DATA |
+-----------------+----------------+
Figure 10-4. Test Registers
31 23 15 11 7 0
+-----------------+---------------+----+-------+-----+-+---+---+
| | |H| | |
| PHYSICAL ADDRESS |0 0 0 0 0 0 0| |REP|0 0| TR7
| | |T| | |
|--------------------------------------+-+-+-+-+-+-+-+-+---+-+-|
| | | |D| |U| |W| | |
| LINEAR ADDRESS |V|D| |U| | | |0 0 0 0|C| TR8
| | | |#| |#| |#| | |
+-----------------+---------------+----+-+-+-+-+-+-+-+-------+-+
NOTE: 0 INDICATES INTEL RESERVED. NO NOT DEFINE
10.6.3 Test Operations
To write a TLB entry:
Be careful not to write duplicate tags; the results of doing so are
undefined.
To look up (read) a TLB entry:
For the purposes of testing, the V bit functions as another bit of
addresss. The V bit for a lookup request should usually be set, so that
uninitialized tags do not match. Lookups with V=0 are unpredictable if any
tags are uninitialized.
prev: 10.5 Initialization Example
next:
Chapter 11 -- Coprocessing and Multiprocessing