NJU School of Computer Science, Digital Logic and Computer Organization Course Experiment
  • Lab 1: Multiplexers
  • Lab 2: Decoders and Encoders
  • Lab 3: Adders and ALUs
  • Lab 4: Counters and Clocks
  • Lab 5: Register File and Memory
  • Lab 6: Shift Registers and Barrel Shifters
  • Lab 7: Finite State Machines and Keyboard Input
  • Lab 8: VGA interface controller’s implementation
  • Lab 9: Character Input Interface
  • Lab 10: CPU Datapath
  • Lab 11: RV32I Single Cycle CPU
  • Lab 12: Computer Systems
NJU School of Computer Science, Digital Logic and Computer Organization Course Experiment
  • Search

© Copyright 2022, Wei Wang, Haijun Wu, Lu Chen.

Built with Sphinx using a theme provided by Read the Docs.